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? semiconductor components industries, llc, 2001 january, 2001 rev. 8 1 publication order number: cs8371/d cs8371 8.0 v/1.0 a, 5.0 v/250 ma dual regulator with independent output enables and nocap the cs8371 is an 8.0 v/5.0 v dual output linear regulator. the 8.0 v 5.0% output sources 1.0 a, while the 5.0 v 5.0% output sources 250 ma. each output is controlled by its own enable lead. setting the enable input high turns on the associated regulator output. holding both enable inputs low puts the ic into sleep mode where current consumption is less than 10 m a. the regulator is protected against overvoltage, shortcircuit and thermal runaway conditions. the device can w ithstand 45 v load dump transients making suitable for use in automotive environments. on's proprietary nocap solution is the first technology which allows the output to be stable without the use of an external capacitor. the cs8371 is available in a 7 lead to220 package with copper tab. the tab can be connected to a heatsink if necessary. features ? two regulated outputs 8.0 v 5.0%; 1.0 a 5.0 v 5.0%; 250 ma ? independent enable for each output ? seperate sense feedback lead for 8.0 v output ? < 10 m a sleep mode current ? fault protection overvoltage shutdown +45 v peak transient voltage short circuit thermal shutdown ? cmos compatible, low current enable inputs http://onsemi.com pin connections and marking diagram device package shipping ordering information 50 units/rail cs8371et7 to220* straight 50 units/rail cs8371etva7 to220* vertical 50 units/rail cs8371etha7 to220* horizontal to220 seven lead t suffix case 821e to220 seven lead tva suffix case 821j to220 seven lead tha suffix case 821h *seven lead. 1 7 1 1 7 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week cs8371 awlyww tab = gnd pin 1. enable 1 2. enable 2 3. v out2 4. gnd 5. sense 6. v cc 7. v out1 1
cs8371 http://onsemi.com 2 figure 1. block diagram + enable 1 trimmed bandgap voltage reference 1.2 v preregulator bias generator thermal shutdown + enable 2 1.2 v + overvoltage shutdown + v cc current limit v out2 gnd nocap current limit sense v out1 absolute maximum ratings* rating value unit power dissipation internally limited enable input voltage range 0.6 to +10 v load current (8.0 v regulator) internally limited load current (5.0 v regulator) internally limited transient peak voltage (31 v load dump @ 14 v v cc ) 45 v storage temperature range 65 to +150 c junction temperature range 40 to +150 c lead temperature soldering: wave solder (through hole styles only) (note 1.) 260 peak c 1. 10 second maximum. *the maximum package power dissipation must be observed.
cs8371 http://onsemi.com 3 electrical characteristics: (40 c t a +85 c, 10.5 v v cc 16 v, enable 1 = enable 2 = 5.0 v, i out1 = i out2 = 5.0 ma, unless otherwise stated.) characteristic test conditions min typ max unit primary output (v out1 ) output voltage i out1 = 1.0 a 7.60 8.00 8.40 v line regulation 10.5 v v cc 26 v 50 mv load regulation 5.0 ma i out1 1.0 a 150 mv sleep mode quiescent current v cc = 14 v, enable 1 = enable 2 = 0 v 0 0.2 10.0 m a quiescent current v cc = 14 v, i out1 = 1.0 a, i out2 = 250 ma 30 ma dropout voltage i out1 = 250 ma i out1 = 1.0 a 1.2 1.5 v v quiescent bias current i out1 = 5.0 ma, enable 2 = 0 v, v cc = 14 v, i q = i cc i out1 i out1 = 1.0 a, enable 2 = 0 v, v cc = 14 v, i q = i cc i out1 10 22 ma ma ripple rejection f = 120 hz, v cc = 14 v with 1.0 v pp ac, c out = 0 m f f = 10 khz, v cc = 14 v with 1.0 v pp ac, c out = 0 m f f = 20 khz, v cc = 14 v with 1.0 v pp ac, c out = 0 m f 90 74 68 db db db current limit v cc = 16 v 1.1 2.5 a overshoot voltage 5.0 ma i reg1 1.0 a 6.0 v output noise 10 hz 100 khz 300 m v rms secondary output (v out2 ) output voltage i out2 = 250 ma 4.75 5.00 5.25 v line regulation 7.0 v v cc 26 v 40 mv load regulation 5.0 ma i out2 250 ma 100 mv dropout voltage i out2 = 5.0 ma i out2 = 250 ma 2.2 2.5 v v quiescent bias current i out2 = 5.0 ma, enable1 = 0 v, v cc = 14 v, i q = i cc i out2 i out2 = 250 ma, enable1 = 0 v, v cc = 14 v, i q = i cc i out2 7.0 8.0 ma ma ripple rejection f = 120 hz, v cc = 14 v with 1.0 v pp ac, c out = 0 m f f = 10 khz, v cc = 14 v with 1.0 v pp ac, c out = 0 m f f = 20 khz, v cc = 14 v with 1.0 v pp ac, c out = 0 m f 90 75 67 db db db current limit v cc = 16 v 270 600 ma overshoot voltage 5.0 ma i reg2 250 ma 4.3 v output noise 10 hz 100 khz 170 m v rms enable function (enable) input current v cc = 14 v, 0 v enable 5.5 v 150 150 m a input voltage low high 0 2.0 0.8 5.0 v v protection circuitry esd threshold human body model 2.0 4.0 kv overvoltage shutdown 24 30 v thermal shutdown guaranteed by design 150 180 c thermal hysteresis 30 c
cs8371 http://onsemi.com 4 package pin description package lead # 7 lead to220 lead symbol function 1 enable 1 enable control for the 8.0 v, 1.0 a output. 2 enable 2 enable control for the 5.0 v, 250 ma output. 3 v out2 5.0 v 5.0%, 250 ma regulated output. 4 gnd ground. 5 sense sense feedback for the primary 8.0 v output. 6 v cc supply voltage, usually from battery. 7 v out1 8.0 v 5.0%, 1.0 a regulated output. typical performance characteristics 85 c 40 ambient temperature ( c) ambient temperature ( c) figure 2. regulator 1 output voltage figure 3. regulator 2 output voltage output current (ma) output current (ma) figure 4. regulator 1 dropout voltage figure 5. regulator 2 dropout voltage 5.00 20 output voltage (v) output voltage (v) 2.5 dropout voltage (v) 50 8.05 8.04 8.03 8.02 8.01 8.00 7.99 7.98 7.97 7.96 7.95 dropout voltage (v) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 20 0 20 40 60 80 100 120 140 0 100 200 500 600 700 800 900 1000 300 400 0 20 40 60 80 100 120 140 40 4.95 4.90 4.85 2.0 1.5 1.0 0.5 0 100 150 200 250 0 v in = 14 v i out = 1.0 a v in = 14 v i out = 250 a 25 c 25 c 85 c 40 c 40 c
cs8371 http://onsemi.com 5 0 reg 1 output current (a) reg 2 output current (ma) figure 6. regulator 1 current limit figure 7. regulator 2 current limit ambient temperature ( c) ambient temperature ( c) figure 8. quiescent current figure 9. quiescent current 10 0 reg 1 output voltage (v) reg 2 output voltage (v) 1.0 quiescent current (ma0 quiescent current ( m a) 9.0 40 ambient temperature ( c) ambient temperature ( c) figure 10. regulator 1 quiescent current figure 11. regulator 2 quiescent current quiescent current (ma) quiescent current (ma) 40 40 4.0 6.0 40 10 9 8 7 6 5 4 3 2 1 0 123 9 8 7 6 5 4 3 2 1 0 100 200 300 400 50 0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 20 0 20 40 60 80 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 200 20406080 5.5 5.0 4.5 4.0 3.5 3.0 200 20406080 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 200 20406080 v in = 14 v t a = 25 c v in = 14 v t a = 25 c enable 1 = 5.0 v enable 2 = 5.0 v v in = 14 v i out1 = 1.0 a i out2 = 250 ma enable 1 = 0 v enable 2 = 0 v v in = 14 v enable 1 = 5.0 v enable 2 = 0 v v in = 14 v enable 1 = 0 v enable 2 = 5.0 v v in = 14 v i out = 5.0 ma i out = 1.0 a i out = 250 ma i out = 5.0 ma
cs8371 http://onsemi.com 6 0 output current (ma) output current (ma) figure 12. regulator 1 load regulation figure 13. regulator 2 load regulation time ( m s) figure 14. regulator 1 startup figure 15. regulator 2 startup 5.02 0 output voltage (v) output voltage (v) enable 1 (v) 8 time (ns) figure 16. regulator 1 line transient response figure 17. regulator 2 line transient response 0 2 0 8.020 7 6 5 4 3 2 1 0 0 1 2 3 4 5 12 1234567891011 reg 1 output voltage (v) 1 0 1 2 10 12 14 16 input voltage (v) output voltage deviation (v) 100 200 300 400 500 600 time ( m s) enable 2 (v) 8 0 7 6 5 4 3 2 1 0 0 1 2 3 4 5 12 1234567891011 reg 2 output voltage (v) time (ns) 0 0.6 0.2 0 0.2 0.4 10 12 14 16 input voltage (v) output voltage deviation (v) 100 200 300 400 500 600 0.4 0.6 8.015 8.010 8.005 8.000 7.995 7.990 7.985 7.980 100 200 300 400 500 600 700 800 900 1000 50 100 150 200 25 0 5.01 5.00 4.99 4.98 4.97 4.96 4.95 4.94 v in = 14 v c out = 0 m f t a = 25 c i out = 5.0 ma c out = 0 m f t a = 25 c i out = 5.0 ma c out = 0 m f t a = 25 c c out = 0 m f t a = 25 c 85 c 85 c 25 c v in = 14 v 25 c 40 c 40 c
cs8371 http://onsemi.com 7 time ( m s) figure 18. regulator 1 load transient response figure 19. regulator 2 load transient response frequency (hz) frequency (hz) figure 20. regulator 1 ripple rejection figure 21. regulator 2 ripple rejection 100 ripple rejection (db) ripple rejection (db) 100 10 output capacitor size ( m f) figure 22. regulator 1 stability output capacitor esr ( w ) .01 5 10 0 5 load current (ma) output voltage deviation (v) 51015202530 1000 3 2 1 0 1 2 3 time ( m s) 0 5 load current (ma) output voltage deviation (mv) 51015202530 250 +500 0 500 80 60 40 20 100 1k 10k 100k 1m 1 80 60 40 20 100 1k 10k 100k 1m 1 1 0 0.1 1 10 100 1000 v in = 14 v c out = 0 m f t a = 25 c v in = 14 v c out = 0 m f t a = 25 c t a = 25 c v in = 14 v c out = 0 m f t a = 25 c v in = 14 v c out = 0 m f t a = 25 c v in = 14 v r esr 1.6 w i out = 5.0 ma to 1.0 a unstable region
cs8371 http://onsemi.com 8 definition of terms dropout voltage the inputoutput voltage differential at which the circuit ceases to regulate against further reduction in input voltage. measured when the output voltage has dropped 100 mv from the nominal value obtained at 14 v input, dropout voltage is dependent upon load current and junction temperature. current limit peak current that can be delivered to the output. input voltage the dc voltage applied to the input terminals with respect to ground. input output differential the voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. line regulation the change in output voltage for a change in the input voltage. the measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. load regulation the change in output voltage for a change in load current at constant chip temperature. long term stability output voltage stability under accelerated lifetest conditions after 1000 hours with maximum rated voltage and junction temperature. output noise voltage the rms ac voltage at the output, with constant load and no input ripple, measured over a specified frequency range. quiescent current the part of the positive input current that does not contribute to the positive load current. the regulator ground lead current. ripple rejection the ratio of the peaktopeak input ripple voltage to the peaktopeak output ripple voltage. temperature stability of v out the percentage change in output voltage for a thermal variation from room temperature to either temperature extreme. figure 23. applications circuit v in gnd enable 1 v out1 v out2 cs8371 tuner ic control c 1 * 0.1 m f 5.0 v 8.0 v * c 1 is required if the regulator is far from the power source filter. enable 2 application notes with seperate control of each output channel, the cs8371 is ideal for applications where each load must be switched independently. in an automotive radio, the 8.0 v output drives the displays and tape drive motors while the 5.0 v output supplies the tuner ic and memory. stability considerations/nocap normally a low dropout or quasilow dropout regulator (or any type requiring a slow lateral pnp in the control loop) necessitates a large external compensation capacitor at the output of the ic. the external capacitor is also used to curtail overshoot, determine startup delay time and load transient response. traditional ldo regulators typically have low unity gain bandwidth, display overshoot and poor ripple rejection. compensation is also an issue because the high frequency load capacitor value, esr (equivalent series resistance) and board layout parasitics all can create oscillations if not properly accounted for. nocap is an on semiconductor exclusive output stage which internally compensates the ldo regulator over temperature, load and line variations without the need for an expensive external capacitor. it incorporates high gain (>80 db) and large unity gain bandwidth (>100 khz) while maintaining many of the characteristics of a singlepole amplifier (large phase margin and no overshoot). nocap is ideally suited for slow switching or steady loads. if the load displays large transient current requirements, such as with high frequency microprocessors, an output storage capacitor may be needed. some large capacitor and small capacitor esr values at the output may
cs8371 http://onsemi.com 9 cause small signal oscillations at the output. this will depend on the load conditions. with these types of loads, a traditional output stage may be better suited for proper operation. output 1 employs nocap. refer to the plots in the typical performance characteristics section for appropriate output capacitor selections for stability if an external capacitor is required by the switching characteristics of the load. output 2 has a darlington npntype output structure and is inherently stable with any type of capacitive load or no capacitor at all. calculating power dissipation in a dual output linear regulator the maximum power dissipation for a dual output regulator (figure 24) is p d(max) v in(max) v out1(min) i out1(max) v in(max) v out2(min) i out2(max) v in(max) iq (1) where: v in(max) is the maximum input voltage, v out1(min) is the minimum output voltage from v out1 , v out2(min) is the minimum output voltage from v out2 , i out1(max) is the maximum output current, for the application, i out2(max) is the maximum output current, for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2) the value of r q ja can be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 24. dual output regulator with key performance parameters labeled. smart regulator control features v out1 i out1 v out2 i out2 v in i in i q heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja : r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it too is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
cs8371 http://onsemi.com 10 package dimensions to220 seven lead t suffix case 821e04 issue c dim a min max min max millimeters 0.600 0.610 15.24 15.49 inches b 0.386 0.403 9.80 10.23 c 0.170 0.180 4.32 4.56 d 0.028 0.037 0.71 0.94 g 0.045 0.055 1.15 1.39 h j 0.018 0.026 0.46 0.66 k 1.028 1.042 26.11 26.47 l 0.355 0.365 9.02 9.27 m 5 nom q 0.142 0.148 3.61 3.75 u 0.490 0.501 12.45 12.72 v 0.045 0.055 1.15 1.39 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include dambar protrusion. allowable protrusion shall be 0.003 (0.076) total in excess of the d dimension at maximum material condition. 5 nom 0.088 0.102 2.24 2.59 a k u l q d g b c m m v m j h seating plane optional chamfer m to220 seven lead tva suffix case 821j02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. a u d g b t m 0.356 (0.014) m q 7 pl q k f j c e t n l m w dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.77 10.54 c 0.160 0.190 4.06 4.82 d 0.023 0.037 0.58 0.94 e 0.045 0.055 1.14 1.40 f 0.540 0.555 13.72 14.10 g 0.050 bsc 1.27 bsc j 0.014 0.022 0.36 0.56 k 0.785 0.800 19.94 20.32 l 0.322 0.337 8.18 8.56 m 0.073 0.088 1.85 2.24 n 0.090 0.115 2.28 2.91 q 0.146 0.156 3.70 3.95 s 0.164 0.179 4.17 4.55 u 0.460 0.475 11.68 12.07 w 33 r s h h 14.48 15.11 0.570 0.595 r 0.289 0.304 7.34 7.72
cs8371 http://onsemi.com 11 to220 seven lead tha suffix case 821h02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. 1. leads maintain a right angle with respect to the package body to with 0.020". a u d g b t m 0.356 (0.014) m q 7 pl q k f j c e t n l m w s dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.77 10.54 c 0.160 0.190 4.06 4.82 d 0.023 0.037 0.58 0.94 e 0.045 0.055 1.14 1.40 f 0.568 0.583 14.43 14.81 g 0.050 bsc 1.27 bsc j 0.015 0.022 0.38 0.56 k 0.728 0.743 18.49 18.87 l 0.322 0.337 8.18 8.56 m 0.101 0.116 2.57 2.95 n 0.090 0.115 2.28 2.91 q 0.146 0.156 3.70 3.95 s 0.150 0.200 3.81 5.08 u 0.460 0.475 11.68 12.07 w 33 package thermal data parameter to220 seven lead unit r q jc typical 2.4 c/w r q ja typical 50 c/w
cs8371 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs8371/d nocap is a trademark of semiconductor components industries, llc (scillc). north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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